The present invention relates to data processing systems and, more particularly, to the control and monitoring of the power supply sources of these systems.
It should also be noted that the teachings of the present invention can be applied directly to power supply sources of complex systems requiring multiple power supply sources such as, for example, industrial robots, process control systems, or even medical intensive care units.
In existing data processing systems, the power supply circuits are controlled and checked by hard-wired logic circuits. These hard-wired logic circuits have a number of disadvantages. For example, they are ill-suited for circuit modifications that may be required, for example, to improve operation; they become very expensive as soon as the functions needed become complicated; and they make it difficult to manufacture data processing systems with modular configurations. Heretofore, these drawbacks have been offset by the advantages inherent in these hard-wired logic circuits.
Today, we are witnessing a major evolution in the architecture of data processing systems.
This evolution in architecture has been made possible by the advances made in the field of semiconductors, particularly the appearance of large-scale integrated (LSI) circuits. In these LSI circuits, so named because of the large number of basic components incorporated in them, an increase has been seen from year to year in the number of basic components in each substrate. This increase in integration density results in numerous advantages in the design of data processing systems:
the logic circuits are faster; PA0 the cost is lower; and PA0 the space requirements are smaller. PA0 new functions are being added and, in particular, multiprocessor systems are finding increased application; PA0 systems are being designed to be modular, since microprogramming allows construction of systems that can evolve in their functions as well as in their capacities; PA0 systems are designed to be more compact, since a larger number of logic circuits can be placed within the same space. PA0 supply increasingly higher outputs at lower voltages; PA0 have the same modularity and the same evolutionary nature as the devices they power; PA0 ensure effective protection for the powered circuits to avoid massive destruction of components; and PA0 solve protocol problems between the power supplies during the various operational phases of the data processing system. PA0 power supply systems which are evolutionary, i.e., whose configurations can be readily modified as a function of variations in the configuration of the data processing system, by very simply changing a module of the system; PA0 improved power systems, i.e., power supply systems which can readily be improved by simply changing the recorded program controlling the microprocessor; and PA0 conversational power supply systems, i.e., one which enables the operator to have a dialogue with the power supply system. PA0 the centralized control of several power supply systems from the console of the data processing system is made possible; PA0 the decentralized control of a power supply system is made possible from a service panel where each source can be accessed; PA0 a general display of the breakdowns occurring in the power supply system(s) being checked is made on the console of the data processing system; PA0 a detailed display of the incidents occurring in the power supply system is made on the service panel of the power supply system; and PA0 a specific operation of the power supply system in the maintenance mode is made possible by a switch, access to which is limited to qualified personnel only. PA0 a control unit (75) including a microprocessor, a set of memories and associated logic circuits to send commands and to receive reports over a control bus (12) serving as a routing circuit for all signals exchanged between said control unit (75) and the units connected thereto and listed below; PA0 a unit called the operation interface unit (74) connected to the control bus (12) and containing a logic circuits required for controlling and checking via signals exchanged over the control bus (12) an operator console (48), a service panel (11), a slave power supply (9), and a primary power supply unit (8) to which said operation interface unit (74) is connected by a plurality of links (43), (40), (39), and (38); PA0 the same number of downstream interface units (51-1, 51-2, 56-1, 56-2, 61-1, 61-2, 66-1, 66-2) required to meet the check and control needs of the power supply system sources, each downstream interface unit being connected to the control bus (12) and containing the logic circuits required to control and check a group of sources to which said downstream interface unit is connected by a link; PA0 a unit called the configuration definition unit (76) connected to control bus (12) and containing an addressable read-only memory in which are defined all the parameters enabling the control unit (75) to know the type and number of sources making up the power supply system; and PA0 a control bus (12) connected in the manner described above and including lines to carry the signals exchanged between the control unit (75) and the units connected to said control bus (12). PA0 in an initial step, the operator activates the reset facilities (163-8) in order to restore to an initial position the address of a first group of bits displayed by the display facilities (163-0 . . . 163-7); PA0 in a second step, the operator, by activating address progression control facilities (163-9), causes the address of the group of bits displayed by the display facilities (163-0 through 163-7) to progress by one step, said display facilities thus displaying a second group of bits; PA0 in the following successive steps the operator causes the address of the displayed groups of bits to progress in a same manner until the last group of bits to be displayed has been reached. PA0 in an initial step, the operator activates the reset facilities (163-8) in order to restore to its initial state the sequence for scanning the addresses of the groups of bits to be displayed, the successful completion of this first stage being indicated by a specific type lighting of the display facilities (163-0 through 163-7); PA0 in a second step, the operator, by activating the address progression control facilities (163-9), orders the display of the first group of bits, said first group of bits being displayed by the display facilities (163-0 through 163-7); PA0 in the following successive steps, the operator causes the address of the displayed groups of bits to progress in the same manner until the last group of bits to be displayed has been reached; PA0 once the last group of bits has been displayed, a reactivation of the address progression facilities (163-9) restores to its initial position the address scanning sequence for the groups to be displayed; PA0 once this resetting has been completed, the display facilities (163-0 through 163-7) light up according to a specific mode of lighting to indicate to the operator that the initial state has been achieved. PA0 a link (187) called the input link (SPCI-IN), which carries, among other signals, all the signals transmitted from the operator console (48) to the operation interface unit (74); and PA0 a link (193) called the output link (SPCI-OUT), which carries, among other signals, all the signals transmitted from the operation interface unit (74) to the operator console (48). PA0 a start-up request link carrying a stored signal (L.0.G.0.N) signifying that the operator has requested a power supply system start-up sequence from the console (48); PA0 a shutdown request link carrying a stored signal (L.0.G.0.FF) signifying that the operator has requested a power supply system shutdown sequence from the console (48); PA0 an input synchronization link carrying a synchronization signal (ENI) signifying to the operation interface unit (74) that the monitor (10) is required to respond to the start-up request if the corresponding signal (L.0.G.0.N) is active, or respond to the shutdown request if the corresponding signal (L.0.G.0.FF) is active. PA0 link checking the receipt of the start-up request carrying the stored start-up request signal (L.0.G.0.N) after passing through the operation interface unit (74); PA0 a link for checking the receipt of the shutdown request carrying the stored shutdown request signal (L.0.G.0.FF) after passing through the operation interface unit (74); and PA0 an end-of-sequence link carrying a synchronization signal (EN.0.SEQC) signifying that the monitor (10) has completed the execution of the sequence requested by the operator. PA0 a start-up request link carrying a stored signal (L.0.G.0.N) signifying that the operator has requested from the console (48) a power supply system start-up sequence; PA0 a shut-down request link carrying a stored (L.0.G.0.FF) signal signifying that the operator has requested from the console (48) a power supply system shut-down sequence; and PA0 an input synchronization link carrying a synchronization signal (ENI) signifying to the operation interface unit (74) that the monitor (10) is required to respond to the start-up request if the corresponding signal (L.0.G.0.N) signal is active, or respond to the shut-down request if the corresponding shut-down signal (L.0.G.0.FF) is active. PA0 a link for checking the receipt of the start-up request carrying the stored start-up request signal (L.0.G.0.N) after it has passed through the operation interface unit (74); PA0 a link for checking the receipt of the shut-down request carrying the stored shut-down request signal (L.0.G.0.FF) after it has passed through the operation interface unit (74); and PA0 an end-of-sequence link carrying a synchronization signal (EN.0./SEQC), signifying that the monitor (10) has completed the execution of the sequence requested by the operator. PA0 a link for checking the propagation of the start-up request carrying the stored (L.0.G.0.N) signal, after it has passed through the operation interface unit of the preceding power supply system, to the input of the operation interface unit of the following power supply system; PA0 a link for checking the propagation of the shut-down request carrying the stored (L.0.G.0.FF) signal, after it has passed through the operation interface unit of the preceding power supply system to the input of the operation interface unit of the following power supply system; and PA0 a sequence control link to transmit the end-of-sequence signal (EN.0.) of the preceding power supply system to the input of the operation interface unit of the following power supply system where it constitutes the synchronization signal (ENI) of the start of the sequence of said following power supply system or the end-of-sequence signal (SEQC), if the preceding power supply system was the last system. PA0 at instant t1 and during a time interval .theta.1, the operator requests a start-up sequence by sending a signal (201-1) (P.0.WER .0.N) through the console (48) circuits; PA0 at instant t2, the console (48), in response to the signal (202-1) (P.0.WER .0.N), causes the power supply system start-up request signal (201) (L.0.G.0.N) to go up and the power supply system shutdown request signal (201-1) (L.0.G.0.FF) to come down; PA0 after a time interval .theta.2, at instant t3, the console (48) transmits a synchronization signal (204-1) (ENI) during a time interval .theta.3 over the input synchronization link to the operation interface unit (74) of the power supply system; PA0 at instant t4, the monitor (10), alerted by the operation interface unit (74) of the power supply system, initiates the power supply system start-upprocess; and PA0 after a time interval .theta.4 required to complete the start-up process, at instant t5, the power supply system indicates the completion of the start-up sequence by sending an end-of-sequence signal (205-1) (EN.0. or SEQC) to the console (48) circuits. PA0 at instant t11, the operator requests a shutdown sequence by sending a signal (203-1) (P.0.WER .0.FF) through the console (48) circuits; PA0 at instant t12, the console (48), in response to the signal (203-1) (P.0.WER .0.FF), causes the power supply system start-up request signal (200-2) (L.0.G.0.N) to comedown and the shutdown request signal (201-2) (L.0.G.0.FF) to go up; PA0 after a time interval, at instant t13, the console (48) transmits a synchronization signal (204-2) (ENI) over the input synchronization link to the power supply system operation interface unit (74); PA0 at instant t14, the monitor (10), alerted by the power supply system operation interface unit (74), starts the power supply system shutdown process; and PA0 upon completion of the shutdown process, at instant t15, the power supply system indicates said completion of the shutdown process by sending an end-of-sequence signal (205-2)(EN.0. or SEQC) to the console (48) circuits. PA0 at instant T1 and during a time interval .theta.1, the operator requests a start-up sequence by sending a signal (201-1) (P.0.WER .0.N) through the console (48) circuits; PA0 at instant t2, the console (48), in response to the signal (202-1) (P.0.WER .0.N) signal, causes the complex-power-supply system start-up request signal (200-1) (L.0.G.0.N) t0 go up and the complex-power-supply system shutdown request to come down; PA0 after a time interval .theta.2, at instant t3, the console (48) transmits during a time interval .theta.3 a synchronization signal (204-1) (ENI) over the input synchronization link to the operation interface unit (74) of the power supply system in the chain; PA0 at instant t4, the monitor (10) of the first operating system, alerted by its operation interface unit (74), initiates the start-up process for the first power supply system in the chain; PA0 after a time interval .theta.4 required for the completion of its start-up process at instant t5, the first power supply system indicates to the second power supply system that it can now initiate the start-up process by sending an end-of-sequence (205-1) (EN.0.) signal to the operation interface unit (179) of the second power supply system, said end-of-sequence signal (205-1) (EN.0.) for the first system being interpreted by the operation interface unit (179) of the second power supply system as a synchronization signal (206-1) (ENI). PA0 this interpreted signal (206-1) (ENI) enables the operation interface unit (179) of the second power supply system to request the monitor to initiate the start-up process; PA0 upon completion of the start-up process, the second power supply system advises the third power supply system by sending an end-of-sequence signal (207-1) (EN.0.) to the operation interface unit (181) of said third power supply system; PA0 the operation interface unit (181), in turn, interprets this end-of-sequence signal (207-1) (EN.0.) as a synchronization signal (208-1) (ENI), said interpreted signal causing the third power supply system to be started up, and so on until the last power supply system in the chain is reached; PA0 when the last power supply system in the chain has completed its start-up process, which also means that all power supply systems have terminated their start-up sequences, said last power supply system sends a general end-of-sequence signal (209-1) (EN.0./SEQC) to the circuits in the console (48) which is thus advised of the successful completion of the start-up process. PA0 at instant t11, the operator requests a shutdown sequence by sending a signal (203-1) (P.0.WER .0.FF) through the console (48) circuits; PA0 at instant t12, the console (48), in response to the signal (203-1) (P.0.WER .0.FF), causes the complex-power-supply system start-up request signal (200-2) (L.0.G.0.N) to come down and the shutdown request signal (201-2) (L.0.G.0.FF) to go up; PA0 after a safeguarding period, at instant t13, the console (48) transmits a synchronization signal (204-2) (ENI) through the input synchronization link to the operation interface unit (74) of the first power supply system in the chain; PA0 at instant t14, the monitor (10) of the first power supply system, alerted by its operation interface unit (74), initiates the shutdown process for the first power supply system; PA0 upon completion of its shutdown process, at instant t15, the first power supply system advises the second power supply system that it can now initiate its shutdown process by sending an end-of-sequence signal (205-2) (EN.0.) to the operation interface unit (179) of the second power supply system, said end-of-sequence signal (205-2) (EN.0.) of the first power supply system being interpreted by the operation interface unit (179) of the second power supply system as a synchronization signal (206-2) (ENI); PA0 said interpreted signal (206-2) (ENI) enables the operation interface unit (179) of the second power supply system to request the monitor to initiate the shutdown process; PA0 upon completion of the shutdown process, the second power supply system so advises the third power supply system by sending an end-of-sequence signal (207-2) (EN.0.) to the operation interface unit (181) of said third power supply system; PA0 the operation interface unit (181), in turn, interprets said end-of-sequence signal (207-2) (EN.0.) as a synchronization signal (208-2) (ENI); said interpreted signal causes the third power supply system to be shut down; and so on and so forth until the last power supply system in the chain is reached; and PA0 when the last power supply system in the chain has completed its shutdown process, which also means that all power supply systems have completed their shutdown sequences, it sends a general end-of-sequence signal (209-2) (EN.0.-SEQC) to the circuits in the console (48), which is thus advised of the successful completion of the shutdown process. PA0 an interface block (235) to match and/or connect the control and check signals (BPC-IN, PIN, C.0.NS.0.LE, ALIM. PRIM) received from the operating devices (9, 18, 11, 48) with the multiplexer-block (236) input circuits; a multiplexer block (236) to select some of the signals applied to its inputs and to transmit said selected signals over the control bus (12) to which it is connected through its outputs, said multiplexer block (236) being addressed by address lines (PMC ADR09, PMC ADR10, PMC ADR15), and the selection criteria being defined by selection lines (PMC ADR00-PMC ADR02), said address lines and said selection lines belonging to the control bus (12). PA0 an interface block (235) to match and/or connect the internal relooping signals (REG) received from the operation interface unit (74) circuits proper with the multiplexer block (236) input circuits; PA0 a multiplexer block (236) to select some of the signals applied to its inputs and to transmit said selected signals over the control bus (12) to which it is connected through its outputs, said multiplexer block (236) being addressed by addres lines (PMC ADR09, PMC ADR10, PMC ADR15) and the selection criteria being defined by selection lines (PMC ADR00-PMC ADR12), said address lines and said selection lines belonging to the control bus (12). PA0 a plurality of operation command storage registers (238, 239, 240, 241, 242) to store the operation commands (REG) to be transmitted to the operating devices (9, 18, 11, 48), the inputs of said operation command storage registers (238, 239, 240, 241, 242) being connected in parallel over the control bus (12), and the contents of said control bus (12) being transferred in response to a command from the monitor to one of the operation command storage registers (238, 239, 240, 241, 242) previously addressed by means of address lines [PMC ADR(00, 02, 09, 10, 15)], the transfer of the contents of the control bus (12) being itself sampled by means of a control line (PMC-MEMW), the outputs of said operation command storage registers (238, 239, 240, 241, 242) being connected to the inputs of the control circuits (243, 244, 245, 246, 247) of the operating devices (9, 8, 11, 48); PA0 a plurality of control circuits (243, 244, 245, 247) for the operating devices (9, 11, 18, 48) to match the commands received from the operation control storage registers (238, 239, 240, 241, 242) with the operating-device control lines (CMD1, CMD2, P.0.UT). PA0 facilities (248) for processing power system opeation state change requests in order to generate, in response to requests (PREG.0.V, PREGUV, L.0.G.0.N, L.0.G.0.FF, ENI, C.0..0.LF1, C.0..0.LF2, C.0..0.LF3, C.0.MREL) transmitted by the operating devices (9, 11, 18, 48), interrupt signals (MCRINT*, INTR1,,INTR2,,INTR5, INTR) transmitted over the interrupt request lines from the control bus (12) to the monitor (10). PA0 an input interface block (350) to match and/or connect the (D IN) signals received from the facilities (intermediate modules AM908), [(52, 53) or (54, 55) or (57, 58) or (59, 60) or (62, 63) or (64, 65) or (67) or (68)] for controlling and checking the sources with the multiplexer block (358) inputs; PA0 a multiplexer block (358) to select certain signals applied to its inputs and to transmit said selected signals over the control bus (12) to which it is connected, said multiplexer block (358) being addressed and the signal selection criteria being defined by the monitor (10) through address lines [PCM ADR (00, 01, 08, 15)]. PA0 an input interface block (350) to match and/or connect the (REG. ET) loopback signals received from the command storage registers (360, 361, 362) with the multiplexer block (358) inputs; PA0 a multiplexer block (358) to select certain signals applied to its inputs and to transmit said selected signals over the control bus (12) to which it is connected, said multiplexer block (358) being addressed and the signal selection criteria being defined by the monitor (10) through address lines [PCM ADR (00, 01, 08, 15)]. PA0 a plurality of service command storage registers (360, 361) to store the commands (REG ET) to be transmitted to the sources, the input of each command register (360, 361, 362) being connected in parallel over the control bus (12), the contents of said control bus (12) being transferred as a result of a command from the monitor (10) to one of the command storage registers (360, 361) which has been previously addressed through address lines [PMC ADR (00, 01, 08, 15)], PA0 the transfer of the control bus (12) contents being itself sampled through a control line (PMC MEMW), the outputs of said command storage registers (360, 361, 362) being connected to the inputs of the control circuits (363, 364); PA0 a plurality of control circuits (363, 364, 365) to match the commands received from the command storage registers (360, 361, 362) with the source control lines (ISM1, ISM2). PA0 a plurality of service command storage registers (362) to store the commands (REG ET) to be transmitted to the devices powered by the sources, the inputs of said command registers (360, 361, 362) being connected in parallel over the control bus (12) and the contents of said control bus (12) being transferred as a result of a command from the monitor (10) to one of the command storage registers (362) which had been previously addressed by means of address lines [PMC ADR (00, 01, 08, 15)], the transfer of the contents of the control bus (12) being itself sampled by means of a control line (PMC MEMW), the outputs of said command storage registers (300, 361, 362) being connected to the control circuit (363, 364) inputs; PA0 a plurality of control circuits (364) to match the commands received from the command storage registers (360, 361, 362) with the control lines of the devices powered by the sources (LSSC1). PA0 a microprocessor (451) with its clock circuit, said microprocessor (451) including an (INTERRUPT) request input (451-1) connected to a request processing block (450) and three outputs (451-2, 451-3, 451-4); a first control and check signal output (451-2) connected to an internal control and check bus (473), a second output (451-3) connected to an internal address bus (464), a third output (451-4) connected to an internal data bus (462); PA0 an internal control and check bus (473) to carry the internal control and check signals (HLDA, REST, WR*, CSI.0., RD*, INTA*, DBS0, DBS1, ALE), as well as the clock signals (SCLK); PA0 an internal address bus (464) to carry the internal addressing signals [TA (08-15)]; PA0 an internal data bus (462) to carry the internal data signals [IDB (00-07)]; PA0 a request processing block (450) to receive the internal requests (PMC-T.0.UT1, PMC-T.0.UT2) and external requests (BPC-REST-IN, BPC-INTR4*; BPC-INTR5*) and to convert them into interrupt requests (REST-IN-10, INTR4, INTR5, INTR0, INTR6), said request processing block (45) receiving the internal requests at its input (450-1) and the external requests at its input/output (450-3) and tansmitting the interrupt signals at its output (450-2) and at its input/output (450-3); PA0 an internal control and check signal processing block (452) to process via said internal control and check signals, signals for the peripheral units (453, 454, 455, 456, 460) placed under the control of the microprocessor (451), said control and check signal processing block (452) including an input (452-1) at which it receives the internal control and check signals, and two outputs (452-2) and (452-3) to which it applies the command signals to said peripheral units; PA0 a data-address routing block (453) to enable the temporary use of the internal data bus (469) to transmit the light loads of the address which the microprocessor (451) wishes to call: this data-address routing block (453) receives PA0 an internal command bus (465) to carry the internal commands to the control unit (75), this internal command bus (465) powered from the output (452-2) of the command processing block (452); PA0 a bus (467) for addresses internal to the control unit (75); this bus (465) is powered via the output (453-3) of the data address routing block (453). PA0 a block preselector (455) to preselect, upon receiving a command from the microprocessor (451), a block from which the microprocessor is requesting a service; this preselector has its input (455-3) connected to the internal address bus (465), its input (455-1) connected to the internal command bus (465) and its output (455-2) connected to the block preselection bus (468); PA0 a block preselection bus (465) to carry the block preselection signals; PA0 a storage block (454) to call into memory the data and certain power supply system operating parameters; this storage block (454) has its input (454-1) connected to the internal command bus (465), its input (454-2) connected to the block preselection bus (468), its input (454-4) to the internal address bus (467) and its output (454-3) to the internal data bus (462). PA0 a second level control block (456) to process the commands to be transmitted to the circuits powered by the power supply system sources; this second level command block (456) has its input (456-1) connected to the block preselection bus (468), its input (456-2) connected to the internal command bus (465) and its output (456-3) connected to the lines (471) for transmitting commands to the circuits powered by the sources; PA0 a first level command block (458) to process the commands to be transmitted to the sources; this first level command block (458) has its input (458-1) connected to the internal command bus (465) and its output (465-2) connected to the lines (465) for transmitting commands to the sources; PA0 an external address buffer-register (459) to call into memory the addressing signals sent by the microprocessor (451) to the peripheral units; the address buffer-register (459) has its input (459-1) connected to the internal address bus (467) and its output (459-2) connected to the external address bus (459); PA0 a device (460) for checking the direction of the data transfer process to route the data either from the external units to the microprocessor (451) in the case of input data, or from the microprocessor (451) to the external units in the case of output data, this device (460) for checking the direction of the data transfer process has its input/output (460-1) connected to the internal data bus (462), its input/output (460-3) connected to the external data bus (472), and its input (460-2) connected to the internal command bus (465);
All of these advantages have enabled manufacturers to make the structure of computers evolve as follows:
However, this evolution in the architecture of data processing systems has resulted in some disadvantages, such as complexity of the power supply units, which must:
It is extremely difficult and costly to develop hard-wired logic circuits that meet these requirements.
Therefore, this invention provides an improved power supply system which utilizes the capabilities offered by microprocessors to control and check, i.e, monitor, power supply units of modern data processing systems and the like. Power supply systems in accordance with the invention, controlled by one or more microprocessors, allow the following:
In the system of the invention, the microprocessor(s), in conjunction with suitable devices is (are) used to obtain functions designed to facilitate this dialogue between the operator and the power supply system, namely: